module round_key_reg_heap(
    input clk,
    input rst_n,
    input write,
    input [3:0]addr,
    input [127:0]din,
    output reg [127:0]dout
);

    reg [15:0] decout;
    wire [15:0] write_reg;
    wire [127:0] regout[0:15];
        
    always @ (addr)
        case(addr)
            4'd0: decout=16'b0000_0000_0000_0001;
            4'd1: decout=16'b0000_0000_0000_0010;
            4'd2: decout=16'b0000_0000_0000_0100;
            4'd3: decout=16'b0000_0000_0000_1000;
            4'd4: decout=16'b0000_0000_0001_0000;
            4'd5: decout=16'b0000_0000_0010_0000;
            4'd6: decout=16'b0000_0000_0100_0000;
            4'd7: decout=16'b0000_0000_1000_0000;
            4'd8: decout=16'b0000_0001_0000_0000;
            4'd9: decout=16'b0000_0010_0000_0000;
            4'd10:decout=16'b0000_0100_0000_0000;
            default:decout = 16'd0;
        endcase

    assign write_reg=decout & {16{write}};
    
    genvar i;
    generate
        for(i=0;i<11;i=i+1)begin : round_key_heap
            reg_128 r(clk,write_reg[i],din,regout[i]);
        end
    endgenerate

    always @ (addr)
        case(addr)
            4'd0: dout = regout[0];
            4'd1: dout = regout[1];
            4'd2: dout = regout[2];
            4'd3: dout = regout[3];
            4'd4: dout = regout[4];
            4'd5: dout = regout[5];
            4'd6: dout = regout[6];
            4'd7: dout = regout[7];
            4'd8: dout = regout[8];
            4'd9: dout = regout[9];
            4'd10:dout = regout[10];
            default:dout = 128'd0;
        endcase


endmodule